Microchip for driving a resonant circuit

ABSTRACT

A microchip ( 300 ) for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna or a piezoelectric transducer, and wherein the microchip ( 300 ) is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising at least an oscillator ( 315 ), a pulse width modulation (PWM) signal generator subsystem ( 329 ), an analogue to digital converter (ADC) subsystem ( 318 ) and a digital to analogue converter (DAC) subsystem ( 327 ).

FIELD

The present invention relates to a microchip for driving a resonantcircuit. The present invention more particularly relates a microchip fordriving a resonant circuit in the form of an LC tank, an antenna or apiezoelectric transducer.

BACKGROUND

Therapeutic aerosol delivery is the mainstay for the treatment ofasthma, chronic obstructive pulmonary disease (COPD) and cysticfibrosis. Therapeutic aerosol also has applications for the treatment ofinfluenza, osteoporosis as well as the delivery of vaccines.

Pulmonary delivery of therapeutics for the treatment of non-respiratorysystemic disease is appealing because of high lung vascularity, a thinblood-alveolar barrier, large surface area, avoidance of gastric enzymesand first-pass hepatic metabolism. It is also appealing because ofimproved patient comfort and adherence. The pulmonary system can beleveraged to deliver antibodies, proteins, pain killers and nucleicacids. The treatment of central nervous system disorders, such astobacco dependence, could be significantly enhanced through theefficient delivery of nicotine to the systematic circulation through thelungs.

The effectiveness of therapeutic aerosol relates to the amount of drugdeposited beyond the oropharyngeal region. The region where the depositoccurs is a function of the inhaled particles size.

The devices currently used for the administration of inhaled drugs aredivided into three categories: nebulizers, metered-dose inhalers, anddry powder inhalers. Nebulizers are typically divided into two types;jet and ultrasonic but in conventional devices both types haveweaknesses and present issues.

Jet nebulizers are based on the Bernoulli principle and producerelatively large droplets that generally deposit in the oropharyngealregion and are therefore not particularly effective. Ultrasonicnebulizers use piezoelectric crystals that vibrate at frequencies,ranging between 1 MHz and 1.7 MHz, transmitting the vibratory energy tothe liquid converting it to aerosol. It is acknowledged that ultrasonicnebulizers are not effective if viscous suspensions or solutions areused and tend to heat the medication, hence destroy the molecules andremove the benefits of inhalation.

There are other applications which require a resonant circuit to bedriven efficiently in an optimal manner at or near the resonantfrequency of the resonant circuit. For instance, a device whichincorporates a resonant circuit in the form of an antenna typicallyneeds to drive the antenna with a precise AC drive signal to enable theantenna to function optimally. In addition, devices which incorporate aresonant circuit in the form an ultrasonic piezoelectric transducer mustproduce an AC drive signal to drive the ultrasonic transducer optimally.

Thus, a need exists in the art for a microchip for driving a resonantcircuit, such as an LC tank, an antenna or a piezoelectric transducer,which seeks to address at least some of the problems described herein.

BRIEF DESCRIPTION OF THE INVENTION

The present invention provides a microchip as claimed in claim 1 orclaim 13 and an apparatus as claimed in claim 16. The present inventionalso provides preferred embodiments as claimed in the dependent claims.

The various examples of this disclosure which are described below havemultiple benefits and advantages over conventional microchips. Thesebenefits and advantages are set out in the description below.

Since the microchips and the apparatus of examples of this disclosureenable higher efficiency operation than conventional microchips andapparatuses, the microchips and apparatuses of examples of thisdisclosure have an environmental benefit due to the reduced powerrequirement.

BRIEF DESCRIPTION OF THE FIGURES

In order that the present disclosure may be more readily understood,preferable embodiments thereof will now be described, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an integrated circuit arrangement ofthis disclosure;

FIG. 2 is a schematic diagram of an integrated circuit of thisdisclosure;

FIG. 3 is a schematic diagram of a pulse width modulation generator ofthis disclosure;

FIG. 4 is timing diagram of an example of this disclosure;

FIG. 5 is timing diagram of an example of this disclosure;

FIG. 6 is a table showing port functions of an example of thisdisclosure;

FIG. 7 is a schematic diagram of an integrated circuit of thisdisclosure;

FIG. 8 is a circuit diagram of an H-bridge of an example of thisdisclosure;

FIG. 9 is a circuit diagram of a current sense arrangement of an exampleof this disclosure;

FIG. 10 is a circuit diagram of an H-bridge of an example of thisdisclosure;

FIG. 11 is a graph showing the voltages during the phases of operationof the H-bridge of FIG. 8 ;

FIG. 12 is a graph showing the voltages during the phases of operationof the H-bridge of FIG. 8 ;

FIG. 13 is a graph showing the voltage and current at a terminal of anultrasonic transducer while the ultrasonic transducer is being driven bythe H-bridge of FIG. 8 ;

FIG. 14 is a schematic diagram showing connections between integratedcircuits of this disclosure;

FIG. 15 is a schematic diagram of an integrated circuit of thisdisclosure; and

FIG. 16 is diagram illustrating the steps of an authentication method ofan example of this disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, concentrations, applicationsand arrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, the attachment of a first feature and a secondfeature in the description that follows may include embodiments in whichthe first feature and the second feature are attached in direct contact,and may also include embodiments in which additional features may bepositioned between the first feature and the second feature, such thatthe first feature and the second feature may not be in direct contact.In addition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

The following disclosure describes representative examples. Each examplemay be considered to be an embodiment and any reference to an “example”may be changed to “embodiment” in the present disclosure.

Referring now to FIG. 1 of the accompanying drawings, a driver device202 comprises a microchip which is referred to herein as a powermanagement integrated circuit or PMIC 300. The PMIC 300 is a microchipfor driving a resonant circuit. The resonant circuit is an LC tank, anantenna or a piezoelectric transducer. In this example, the resonantcircuit is an ultrasonic transducer 215 which is provided within aresonant circuit device 201. In this example, the resonant circuitdevice 201 is a separate device which is releasably coupled to thedriver device 202. In other examples, the elements of the resonantcircuit device 201 are combined in the same device as the driver device202.

In this disclosure, the terms chip, microchip and integrated circuit areinterchangeable. The microchip or integrated circuit is a single unitwhich comprises a plurality of interconnected embedded components andsubsystems. The microchip is, for example, at least partly of asemiconductor, such as silicon, and is fabricated using semiconductormanufacturing techniques.

This disclosure describes an example resonant circuit device 201 whichis a mist inhaler device which comprises an ultrasonic transducer 215.When the ultrasonic transducer 215 is activated by the driver device202, the ultrasonic transducer 215 atomises a liquid to generate a mistfor inhalation by a user.

However, it is to be appreciated that the elements of the driver deviceare used differently in other applications involving a resonant circuit.In these other examples, the ultrasonic transducer 215 is replaced withanother resonant circuit, such as LC tank or an antenna.

In one example, the resonant circuit device 201 comprises a resonantcircuit in the form of a piezoelectric ultrasonic transducer whichgenerates ultrasonic waves that are used for wireless power transfer. Inthis example, the ultrasonic transducer is driven by the driver device202 to generate ultrasonic waves that can be focused and sent to areceiver transducer. The receiver transducer converts the ultrasonicwaves back into electrical energy and stores the energy in an energystorage device, such as a battery, or uses the electrical energy topower a device. In this way, a device can be remotely charged or poweredvia the power which is transferred wirelessly via the ultrasonic waveswithout the device having to be tethered to an electrical outlet.

As described below, the driver device 202 is configured to modulate thefrequency and duty cycle of the AC power signal driving an ultrasonictransducer with high accuracy and efficiency. In the case of a powertransfer system, this enables the driver device 202 to encodeinformation for wireless transmission by modulating the ultrasonic waveswhich carry the encoded information. In one example, the driver device202 is configured for use in a wireless power transfer system such asbut not limited to the type described in U.S. Pat. No. 9,001,622entitled “receiver communications for wireless power transfer” which isincorporated herein by reference in its entirety.

In another example, the driver device 202 drives a resonant circuit inthe form of an ultrasonic transducer for delivering ultrasonic waves ata precise frequency and at high intensity to treat tumours. Thehigh-intensity focused ultrasound from the ultrasonic transducer is usedas a non-invasive targeted treatment to raise the temperature within atumour to above 65° C., killing the cells of the tumour without damagingthe surrounding tissue.

In a further application, the driver device 202 is used to drive aresonant circuit in the form an antenna to control the frequency andpower of waves transmitted by the antenna accurately. In this example,the antenna may be used for any purpose. In one example, the driverdevice 202 drives an antenna to transmit waves at a precise frequencyfor the purpose of searching for materials, such as minerals or gold inthe ground.

The driver device 202 comprises a second microchip which is referred toherein as a bridge integrated circuit or bridge IC 301 which iselectrically connected to the PMIC 300.

The bridge IC 301 is a microchip for driving a resonant circuit, such asan LC tank, an antenna or a piezoelectric transducer. The bridge IC 301is a single unit which comprises a plurality of interconnected embeddedcomponents and subsystems.

In this example, the PMIC 300 and the bridge IC 301 are mounted to thesame PCB of the driver device 202. In this example, the physicaldimensions of the PMIC 300 are 1-3 mm wide and 1-3 mm long and thephysical dimensions of the bridge IC 301 are 1-3 mm wide and 1-3 mmlong.

In this example, the resonant circuit device 201 comprises an optionalprogrammable or one time programmable integrated circuit or OTP IC 242.When the resonant circuit device 201 is coupled to the driver device202, the OTP IC is electrically connected to the PMIC 300 to receivepower from the PMIC 300 such that the PMIC 300 can manage the voltagesupplied to the OTP IC 242. The OTP IC 242 is also connected to acommunication bus 302 in the driver device 202. In this example, thecommunication bus 302 is an I2C bus but in other examples thecommunication bus 302 is another type of digital serial communicationbus.

The OTP IC 242 provides a security function which is described below.However, it is to be appreciated that the OTP IC 242 is omitted inexamples of this disclosure which do not require such a securityfunction.

The ultrasonic transducer 215 in the resonant circuit device 201 iselectrically connected to the bridge IC 301 so that the ultrasonictransducer 215 may be driven by an AC drive signal generated by thebridge IC 301 when the device 200 is in use.

The driver device 202 comprises a processor in the form of amicrocontroller 303 which is electrically coupled for communication withthe communication bus 302. In this example, the microcontroller 303 is aBluetooth™ low energy (BLE) microcontroller but in other examples themicrocontroller 303 is a general purpose processor. The microcontroller303 receives power from a low dropout regulator (LDO) 304 which isdriven by the battery 250. The LDC 304 provides a stable regulatedvoltage to the microcontroller 303 to enable the microcontroller 303 tooperate consistently even when there is a variation in the voltage ofthe battery 250.

The driver device 202 comprises a voltage regulator in the form a DC-DCboost converter 305 which is powered by the battery 250. The boostconverter 305 increases the voltage of the battery 250 to a programmablevoltage VBOOST. The programmable voltage VBOOST is set by the boostconverter 305 in response to a voltage control signal VCTL from the PMIC300, As will be described in more detail below, the boost converter 305outputs the voltage VBOOST to the bridge IC 301. In other examples, thevoltage regulator is a buck converter or another type of voltageregulator which outputs a selectable voltage.

The voltage control signal VCTL is generated by a digital to analogueconverter (DAC) which, in this example, is implemented within the PMIC300. The DAC is not visible in FIG. 1 since the DAC is integrated withinthe PMIC 300. The DAC and the technical benefits of integrating the DACwithin the PMIC 300 are described in detail below.

In this example, the PMIC 300 is connected to a power source connectorin the form of a universal serial bus (USB) connector 306 so that thePMIC 300 can receive a charging voltage VCHRG when the USB connector 306is coupled to a USB charger.

In this example, the driver device 202 comprises a first pressure sensor307 which, in this example, is a static pressure sensor. The driverdevice 202 also comprises a second pressure sensor 308 which, in thisexample, is a dynamic pressure sensor. However, in other examples, thedriver device 202 comprises only one of the two pressure sensors 307,308 or the pressure sensors 307, 308 are omitted entirely. In thisexample, which relates to a mist generator device, the pressure sensors307, 308 sense a change in the pressure in an aerosol chamber (notshown) to sense when a user is drawing mist from the aerosol chamber.

In this example, the driver device 202 comprises a plurality of LEDs 308which are controlled by the PMIC 300. In other examples, the LEDs 308are omitted.

The microcontroller 303 functions as a master device on thecommunication bus 302, with the PMIC 300 being a first slave device, theOTP IC 242 being a second slave device, the second pressure sensor 308being a third slave device and the first pressure sensor 307 being the afourth slave device. The communication bus 302 enables themicrocontroller 303 to control the following functions within the driverdevice 202:

-   -   1. All functions of the PMIC are highly configurable by the        microcontroller 303.    -   2. The current flowing through the resonant circuit (ultrasonic        transducer 215) is sensed by a high bandwidth sense and        rectifier circuit at a high common mode voltage (high side of        the bridge). The sensed current is converted into a voltage        proportional to the rms current and provided as a buffered        voltage at a current sense output pin 309 of the bridge IC 301.        This voltage is fed to and sampled in the PMIC 300 and made        available as a digital representation via I2C requests. Sensing        the current flowing through the ultrasonic transducer 215 forms        part of the resonant frequency tracking functionality. As        described herein, the ability of the device to enable this        functionality within the bridge IC 301 provides significant        technical benefits.    -   3. The DAC (not shown in FIG. 1 ) integrated within the PMIC 300        enables the DC-DC boost converter voltage VBOOST to be        programmed to be between 10V and 20V.    -   4. The microcontroller 303 enables the charger sub-system of the        device 202 to manage the charging of a battery, which in this        example is a single cell battery.    -   5. A Light Emitting Diode (LED) driver module (not shown) is        powered by the PMIC 300 to drive and dim digitally the LEDs 308        either in linear mode or in gamma corrected mode.    -   6. The microcontroller 303 is able to read Pressure#1 and        Pressure#2 sensor values from the pressure sensors 307, 308.

Referring now to FIG. 2 of the accompanying drawings, the PMIC 300 is,in this example, a self-contained chip or integrated circuit whichcomprises integrated subsystems and a plurality of pins which provideelectrical inputs and outputs to the PMIC 300. The references to anintegrated circuit or chip in this disclosure are interchangeable andeither term encompasses a semiconductor device which may, for instance,be of silicon.

The PMIC 300 comprises an analogue core 310 which comprises analoguecomponents including a reference block (BG) 311, a LDO 312, a currentsensor 313, a temperature sensor 314 and an oscillator 315.

As described in more detail below, the oscillator 315 is coupled to adelay locked loop (DLL) which outputs pulse width modulation (PWM)phases A and B. The oscillator 315 and the DLL generate a two phasecentre aligned PWM output which drives an H bridge in the bridge IC 301.

The DLL comprises a plurality of delay lines connected end to end,wherein the total delay of the delay lines is equal to the period of themain clock signal clk_m. In this example, the DLL is implemented in adigital processor subsystem, referred to herein as a digital core 316,of the PMIC 300 which receives a clock signal from the oscillator 315and a regulated power supply voltage from the LDO 312. The DLL isimplemented in a large number (e.g. in the order of millions) of delaygates which are connected end to end in the digital core 316.

The implementation of the oscillator 315 and the DLL in the sameintegrated circuit of the PMIC 300 in order to generate a two phasecentre aligned PWM signal is unique since at present no signal generatorcomponent in the integrated circuit market comprises thisimplementation.

As described herein, PWM is part of the functionality which enables thedriver device 202 to track the resonant frequency of the ultrasonictransducer 215 accurately in order to maintain an efficient transferfrom electrical energy to kinetic energy in order to optimise thegeneration of mist. The same functionality enables other examples whichcomprise a different resonant circuit by driving the resonant circuitefficiently and at a high power and a high frequency.

In this example, the PMIC 300 comprises a charger circuit 317 whichcontrols the charging of the battery 250, for instance by power from aUSB power source. The charger circuit 317 is omitted in other exampleswhich do not require a battery.

The PMIC 300 comprises an integrated power switch VSYS which configuresthe PMIC 300 to power the analogue core 310 by power from the battery250 or by power from an external power source if the battery 250 isbeing charged.

The PMIC 300 comprises an embedded analogue to digital converter (ADC)subsystem 318. The implementation of the ADC 318 together with theoscillator 315 in the same integrated circuit is, in itself, uniquesince there is no other integrated circuit in the integrated circuitmarket which comprises an oscillator and an ADC implemented assub-blocks within the integrated circuit. In a conventional device, anADC is typically provided as a separate discrete component from anoscillator with the separate ADC and oscillator being mounted to thesame PCB. The problem with this conventional arrangement is that the twoseparate components of the ADC and the oscillator take up spaceunnecessarily on the PCB. A further problem is that the conventional ADCand oscillator are usually connected to one another by a serial datacommunication bus, such as an I2C bus, which has a limited communicationspeed of up to only 400 kHz. In contrast to conventional devices, thePMIC 300 comprises the ADC 318 and the oscillator 315 integrated withinthe same integrated circuit which eliminates any lag in communicationbetween the ADC 318 and the oscillator 315, meaning that the ADC 318 andthe oscillator 315 can communicate with one another at high speed, suchas at the speed of the oscillator 315 (e.g. 3 MHz to 5 MHz).

In the PMIC 300 of this example, the oscillator 315 is running at 5 MHzand generates a clock signal SYS CLOCK at 5 MHz. However, in otherexamples, the oscillator 315 generates a clock signal at a much higherfrequency of up to 105 MHz. The integrated circuits described herein areall configured to operate at the high frequency of the oscillator 315.

The ADC 318 comprises a plurality of feedback input terminals oranalogue inputs 319 which comprise a plurality of GPIO inputs(IF_GPIO1-3). At least one of the feedback input terminals or theanalogue inputs 319 receives a feedback signal from an H-bridge circuitin the bridge IC 301, the feedback signal being indicative of aparameter of the operation of the H-bridge circuit or an AC drive signalwhen the H-bridge circuit is driving a resonant circuit, such as theultrasonic transducer 215, with the AC drive signal. As described below,the GPIO inputs are used to receive a current sense signal from thebridge IC 301 which is indicative of the route mean square (rms) currentreported by the bridge IC 301. In this example, one of the GPIO inputsis a feedback input terminal which receives a feedback signal from theH-bridge in the bridge IC 301.

The ADC subsystem 318 samples analogue signals received at the pluralityof ADC input terminals 319 at a sampling frequency which is proportionalto the frequency of the main clock signal. The ADC subsystem 318 thengenerates ADC digital signals using the sampled analogue signals.

In this example, the ADC 318 which is incorporated in the PMIC 300samples not only the RMS current flowing through the H-bridge 334 andthe ultrasonic transducer 215 but also voltages available in the system(e.g. VBAT, VCHRG, VBOOST), the temperature of the PMIC 300, thetemperature of the battery 250 and the GPIO inputs (IF_GPIO1-3) whichallow for future extensions.

The digital core 316 receives the ADC generated digital signals from theADC subsystem and processes the ADC digital signals to generate thedriver control signal. The digital core 316 communicates the drivercontrol signal to the PWM signal generator subsystem (DLL 332) tocontrol the PWM signal generator subsystem.

Rectification circuits existing in the market today have a very limitedbandwidth (typically less than 1 MHz). Since the oscillator 315 of thePMIC 300 is running at up to 5 MHz or even up to 105 Mhz, a highbandwidth rectifier circuit is implemented in the PMIC 300. As will bedescribed below, sensing the RMS current within an H bridge of thebridge IC 301 forms part of a feedback loop which enables the driverdevice 202 to drive the ultrasonic transducer 215 with high precision.The feedback loop is a game changer in the industry of drivingultrasound transducers since it accommodates for any process variationin the piezo electric transducer production (variations of resonancefrequencies) and it compensates for temperature effects of the resonancefrequency. This is achieved, in part, by the inventive realisation ofintegrating the ADC 318, the oscillator 315 and the DLL within the sameintegrated circuit of the PMIC 300. The integration enables thesesub-systems to communicate with one another at high speed (e.g. at theclock frequency of 5 MHz or up to 105 MHz). Reducing the lag betweenthese subsystems is a game changer in the ultrasonics industry,particularly in the field of mist generator devices.

The ADC 318 comprises a battery voltage monitoring input VBAT and acharger input voltage monitoring input VCHG as well as voltagemonitoring inputs VMON and VRTH as well as a temperature monitoringinput TEMP.

The temperature monitoring input TEMP receives a temperature signal fromthe temperature sensor 314 which is embedded within the PMIC 300. Thisenables the PMIC 300 to sense the actual temperature within the PMIC 300accurately so that the PMIC 300 can detect any malfunction within thePMIC 300 as well as malfunction to other components on the printedcircuit board which affect the temperature of the PMIC 300. The PMIC 300can then control the bridge IC 301 to prevent excitation of theultrasonic transducer 215 if there is a malfunction in order to maintainthe safety of the resonant circuit device 201.

The additional temperature sensor input VRTH receives a temperaturesensing signal from an external temperature sensor within the driverdevice 202 which monitors the temperature of a battery. The PMIC 300 canthus react to stop the battery from being charged in the event of a highbattery temperature or otherwise shut down the driver device 202 inorder to reduce the risk of damage being caused by an excessively highbattery temperature.

The PMIC 300 comprises an LED driver 320 which, in this example,receives a digital drive signal from the digital core 316 and providesLED drive output signals to six LEDs 321-326 which are configured to becoupled to output pins of the PMIC 300. The LED driver 320 can thusdrive and dim the LEDs 321-326 in up to six independent channels.

The PMIC 300 comprises a first digital to analogue converter (DAC) 327which converts digital signals within the PMIC 300 into an analoguevoltage control signal which is output from the PMIC 300 via an outputpin VDAC0. The first DAC 327 converts a digital control signal generatedby the digital core 316 into an analogue voltage control signal which isoutput via the output pin VDAC0 to control a voltage regulator circuit,such as the boost converter 305. The voltage control signal thuscontrols the voltage regulator circuit to generate a predeterminedvoltage for modulation by the H-bridge circuit to drive a resonantcircuit, such as the ultrasonic transducer 215, in response to feedbacksignals which are indicative of the operation of the resonant circuit(the ultrasonic transducer 215).

In this example, the PMIC 300 comprises a second DAC 328 which convertsdigital signals within the PMIC 300 into an analogue signal which isoutput from the PMIC 300 via a second analogue output pin VDAC1.

Embedding the DAC 327 or the DACs 327, 328 within the same microchip asthe other subsystems of the PMIC 300 allows the DACs 327, 328 tocommunicate with the digital core 316 and other components within thePMIC 300 at high speed with no or minimal communication lag. The DACs327, 328 provide analogue outputs which control external feedback loops.For instance, the first DAC 327 provides the control signal VCTL to theboost converter 305 to control the operation of the boost converter 305.In other examples, the DACs 327, 328 are configured to provide a drivesignal to a DC-DC buck converter instead of or in addition to the boostconverter 305. Integrating the two independent DAC channels in the PMIC300 enables the PMIC 300 to manipulate the feedback loop of anyregulator used in the driver device 202 and allows the driver device 202to regulate the sonication power of the ultrasonic transducer 215 or toset analogue thresholds for absolute maximum current and temperaturesettings of the ultrasonic transducer 215.

The PMIC 300 comprises a serial communication interface which, in thisexample, is an I2C interface which incorporates external I2C address setthrough pins.

The PMIC 300 also comprises various functional blocks which include adigital machine (FSM) to implement the functionality of the microchip.These blocks will be described in more detail below.

Referring now to FIG. 3 of the accompanying drawings, a pulse widthmodulation (PWM) signal generator subsystem 329 is embedded within thePMIC 300. The PWM generator system 329 comprises the oscillator 315, andfrequency divider 330, a multiplexer 331 and a delay locked loop (DLL)332. As will be described below, the PWM generator system 329 is a twophase centre aligned PWM generator.

The frequency divider 330, the multiplexer 331 and the DLL 332 areimplemented in digital logic components (e.g. transistors, logic gates,etc.) within the digital core 316.

In examples of this disclosure, the frequency range which is covered bythe oscillator 315 and respectively by the PWM generator system 329 is50 kHz to 5 MHz or up to 105 MHz. The frequency accuracy of the PWMgenerator system 329 is ±1% and the spread over temperature is ±1%. Inthe IC market today, no IC has an embedded oscillator and two phasecentre aligned PWM generator that can provide a frequency range of 50kHz to 5 MHz or up to 105 MHz.

The oscillator 315 generates a main clock signal (clk_m) with afrequency of 50 kHz to 5 MHz or up to 105 MHz. The main clock clk_m isinput to the frequency divider 330 which divides the frequency of themain clock clk_m by one or more predetermined divisor amounts. In thisexample, the frequency divider 330 divides the frequency of the mainclock clk_m by 2, 4, 8 and 16 and provides the divided frequency clocksas outputs to the multiplexer 331. The multiplexer 331 multiplexes thedivided frequency clocks and provides a divided frequency output to theDLL 332. This signal which is passed to the DLL 332 is a frequencyreference signal which controls the DLL 332 to output signals at adesired frequency. In other examples, the frequency divider 330 and themultiplexer 331 are omitted.

The oscillator 315 also generates two phases; a first phase clock signalPhase 1 and a second phase clock signal Phase 2. The phases of the firstphase clock signal and the second phase clock signal are centre aligned.As illustrated in FIG. 4 :

-   -   The first phase clock signal Phase 1 is high for a variable time        of clk_m's positive half-period and low during clk_m's negative        half-period.    -   The second phase clock signal Phase 2 is high for a variable        time of clk_m's negative half-period and low during clk_m's        positive half-period.

Phase 1 and Phase 2 are then sent to the DLL 332 which generates adouble frequency clock signal using the first phase clock signal Phase 1and the second phase clock signal Phase 2. The double frequency clocksignal is double the frequency of the main clock signal clk_m. In thisexample, an “OR” gate within the DLL 332 generates the double frequencyclock signal using the first phase clock signal Phase 1 and the secondphase clock signal Phase 2. This double frequency clock or the dividedfrequency coming from the frequency divider 330 is selected based on atarget frequency selected and then used as reference for the DLL 332.

Within the DLL 332, a signal referred to hereafter as “clock” representsthe main clock clk_m multiplied by 2, while a signal referred tohereafter as “clock_del” is a replica of clock delayed by one period ofthe frequency. Clock and clock_del are passed through a phase frequencydetector. A node Vc is then charged or discharged by a charge-pump basedon the phase error polarity. A control voltage is fed directly tocontrol the delay of every single delay unit within the DLL 332 untilthe total delay of the DLL 332 is exactly one period.

The DLL 332 controls the rising edge of the first phase clock signalPhase 1 and the second phase clock signal Phase 2 to be synchronous withthe rising edge of the double frequency clock signal. The DLL 332adjusts the frequency and the duty cycle of the first phase clock signalPhase 1 and the second phase clock signal Phase 2 in response to arespective frequency reference signal and a duty cycle control signal toproduce a first phase output signal Phase A and a second phase outputsignal Phase B to drive an H-bridge or an inverter to generate an ACdrive signal to drive an ultrasonic transducer.

The PMIC 300 comprises a first phase output signal terminal PHASE_Awhich outputs the first phase output signal Phase A to an H-bridgecircuit and a second phase output signal terminal PHASE_B which outputsthe second phase output signal Phase B to an H-bridge circuit.

In this example, the DLL 332 adjusts the duty cycle of the first phaseclock signal Phase 1 and the second phase clock signal Phase 2 inresponse to the duty cycle control signal by varying the delay of eachdelay line in the DLL 332 response to the duty cycle control signal.

The clock is used at double of its frequency because guarantees betteraccuracy. As shown in FIG. 5 , for the purpose of explanation if thefrequency of the main clock clk_m is used (which it is not in examplesof this disclosure), Phase A is synchronous with clock's rising edge R,while Phase B is synchronous with clock's falling edge F. The delay lineof the DLL 332 controls the rising edge R and so, for the falling edgeF, the PWM generator system 329 would need to rely on a perfect matchingof the delay units of the DLL 332 which can be imperfect. However, toremove this error, the PWM generator system 329 uses the doublefrequency clock so that both Phase A and Phase B are synchronous withthe rising edge R of the double frequency clock.

To perform a duty-cycle from 20% to 50% with a 2% step size, the delayline of the DLL 332 comprises 25 delay units, with the output of eachrespective delay unit representing a Phase nth. Eventually the phase ofthe output of the final delay unit will correspond to the input clock.Considering that all delays will be almost the same, a particular dutycycle is obtained with the output of the specific delay unit with simplelogic in the digital core 316.

It is important to take care of the DLL 332 startup as the DLL 332 mightnot be able to lock a period of delay but two or more periods, takingthe DLL 332 to a non-convergence zone. To avoid this issue, a start-upcircuit is implemented in the PWM generator system 329 which allows theDLL 332 to start from a known and deterministic condition. The start-upcircuit furthermore allows the DLL 332 to start with the minimum delay.

In examples of this disclosure, the frequency range covered by the PWMgenerator system 329 is extended and so the delay units in the DLL 332can provide delays of 4 ns (for an oscillator frequency of 5 MHz) to 400ns (for an oscillator frequency of 50 kHz). In order to accommodate forthese differing delays, capacitors Cb are included in the PWM generatorsystem 329, with the capacitor value being selected to provide therequired delay.

The Phase A and Phase B are output from the DLL 332 and passed through adigital IO to the bridge IC 301 so that the Phase A and Phase B can beused to control the operation of the bridge IC 301.

The battery charging functionality of the driver device 202 will now bedescribed in more detail. The battery charging sub-system comprises thecharger circuit 317 which is embedded in the PMIC 300 and controlled bya digital charge controller hosted in the PMIC 300. The charger circuit317 is controlled by the microcontroller 303 via the communication bus302. The battery charging sub-system is able to charge a single celllithium polymer (LiPo) or lithium-ion (Li-ion) battery.

In this example, the battery charging sub-system is able to charge abattery or batteries with a charging current of up to 1 A from a 5Vpower supply (e.g. a USB power supply). One or more of the followingparameters can be programmed through the communication bus 302 (I2Cinterface) to adapt the charge parameters for the battery:

-   -   Charge voltage can be set between 3.9V and 4.3V in 100 mV steps.    -   The charge current can be set between 150 mA and 1000 mA in 50        mA steps.    -   The pre-charge current is 1/10 of the charge current.    -   Pre-charge and fast charge timeouts can be set between 5 and 85        min respectively 20 and 340 min.    -   Optionally an external negative temperature coefficient (NTC)        thermistor can be used to monitor the battery temperature.

In some examples, the battery charging sub-system reports one or more ofthe following events by raising an interrupt to the host microcontroller303:

-   -   Battery detected    -   Battery is being charged    -   Battery is fully charged    -   Battery is not present    -   Charge timeout reached    -   Charging supply is below the undervoltage limit

The main advantage of having the charger circuit 317 embedded in thePMIC 300, is that it allows all the programming options and eventindications listed to be implemented within the PMIC 300 whichguarantees the safe operation of the battery charging sub-system.Furthermore, a significant manufacturing cost and PCB space saving canbe accomplished compared with conventional resonant circuit devices,such as mist inhaler devices, which comprise discrete components of acharging system mounted separately on a PCB. The charger circuit 317also allows for highly versatile setting of charge current and voltage,different fault timeouts and numerous event flags for detailed statusanalysis.

The analogue to digital converter (ADC) 318 will now be described inmore detail. The inventors had to overcome significant technicalchallenges to integrate the ADC 318 within the PMIC 300 with the highspeed oscillator 315. Moreover, integrating the ADC 318 within the PMIC300 goes against the conventional approach in the art which relies onusing one of the many discrete ADC devices that are available in the ICmarket.

In this example, the ADC 318 samples at least one parameter within theultrasonic transducer driver chip (PMIC 300) at a sampling rate which isequal to the frequency of the main clock signal clk_m. In this example,the ADC 318 is a 10 bit analogue to digital converter which is able tounload digital sampling from the microprocessor 303 to save theresources of the microprocessor 303. Integrating the ADC 318 within thePMIC 300 also avoids the need to use an I2C bus that would otherwiseslow down the sampling ability of the ADC (a conventional device relieson an I2C bus to communicate data between a dedicated discrete ADC and amicrocontroller at a limited clock speed of typically up to 400 kHz).

In examples of this disclosure, one or more of the following parameterscan be sampled sequentially by the ADC 318:

-   -   i. An rms current signal which is received at the ultrasonic        transducer driver chip (PMIC 300) from an external inverter        circuit which is driving an ultrasonic transducer. In this is        example, this parameter is a root mean square (rms) current        reported by the bridge IC 301. Sensing the rms current is        important to implementing the feedback loop used for driving the        ultrasound transducer 215. The ADC 318 is able to sense the rms        current directly from the bridge IC 301 via a signal with        minimal or no lag since the ADC 318 does not rely on this        information being transmitted via an I2C bus. This provides a        significant speed and accuracy benefit over conventional devices        which are constrained by the comparatively low speeds of an I2C        bus.    -   ii. The voltage of a battery connected to the PMIC 300.    -   iii. The voltage of a charger connected to the PMIC 300.    -   iv. A temperature signal, such as a temperature signal which is        indicative of the PMIC 300 chip temperature. As described above,        this temperature can be measured very accurately due to the        temperature sensor 314 being embedded in the same IC as the        oscillator 315. For example, if the PMIC 300 temperature goes        up, the current, frequency and PWM are regulated by the PMIC 300        to control the transducer oscillation which in turn controls the        temperature.    -   v. Two external pins.    -   vi. External NTC temperature sensor to monitor battery pack        temperature.

In some examples, the ADC 318 samples one or more of the above-mentionedsources sequentially, for instance in a round robin scheme. The ADC 318samples the sources at high speed, such as the speed of the oscillator315 which may be up to 5 MHz or up to 105 MHz.

In some examples, the device 202 is configured so that a user or themanufacturer of the device can specify how many samples shall be takenfrom each source for averaging. For instance, a user can configure thesystem to take 512 samples from the rms current input, 64 samples fromthe battery voltage, 64 from the charger input voltage, 32 samples fromthe external pins and 8 from the NTC pin. Furthermore, the user can alsospecify if one of the above-mentioned sources shall be skipped.

In some examples, for each source the user can specify two digitalthresholds which divide the full range into a plurality of zones, suchas 3 zones. Subsequently the user can set the system to release aninterrupt when the sampled value changes zones e.g. from a zone 2 to azone 3.

No conventional IC available in the market today can perform the abovefeatures of the PMIC 300. Sampling with such flexibility and granularityis paramount when driving a resonant circuit or component, such as anultrasound transducer.

In this example, the PMIC 300 comprises an 8 bit general purpose digitalinput output port (GPIO). Each port can be configured as digital inputand digital output. Some of the ports have an analogue input function,as shown in the table in FIG. 6 .

The GPIO7-GPIO5 ports of the PMIC 300 can be used to set the device'saddress on the communication (I2C) bus 302. Subsequently eight identicaldevices can be used on the same I2C bus. This is a unique feature in theIC industry since it allows eight identical devices to be used on thesame I2C bus without any conflicting addresses. This is implemented byeach device reading the state of GPIO7-GPIO5 during the first 100 μsafter the startup of the PMIC 300 and storing that portion of theaddress internally in the PMIC 300. After the PMIC 300 has been startedup the GPIOs can be used for any other purpose.

As described above, the PMIC 300 comprises a six channel LED driver 320.In this example the LED driver 320 comprises N-Channel Metal-OxideSemiconductor (NMOS) current sources which are 5V tolerant. The LEDdriver 320 is configured to set the LED current in four discrete levels;5 mA, 10 mA, 15 mA and 20 mA. The LED driver 320 is configured to dimeach LED channel with a 12 bit PWM signal either with or without gammacorrection. The LED driver 320 is configured to vary the PWM frequencyfrom 300 Hz to 1.5 KHz. This feature is unique in the field of resonantcircuit devices, such as ultrasonic mist inhaler devices, as thefunctionality is embedded as a sub-system of the PMIC 300.

In this example, the PMIC 300 comprises two independent 6 Bit Digital toAnalog Converters (DAC) 327, 328 which are incorporated into the PMIC300. The purpose of the DACs 327, 328 is to output an analogue voltageto manipulate the feedback path of an external regulator (e.g. the DC-DCBoost converter 305 a Buck converter or a LDO). Furthermore, in someexamples, the DACs 327, 328 can also be used to dynamically adjust theover current shutdown level of the bridge IC 301, as described below.

The output voltage of each DAC 327, 328 is programmable between 0V and1.5V or between 0V and V_battery (Vbat). In this example, the control ofthe DAC output voltage is done via I2C commands. Having two DACincorporated in the PMIC 300 is unique and will allow the dynamicmonitoring control of the current. If either DAC 327, 328 was anexternal chip, the speed would fall under the same restrictions of speedlimitations due to the I2C protocol. An active power monitoringarrangement of the device 202 works with optimum efficiency if all theseembedded features are in the PMIC. Had they been external components,the active power monitoring arrangement would be totally inefficient.

Referring now to FIG. 7 of the accompanying drawings, the bridge IC 301is a microchip which comprises an embedded power switching circuit 333.In this example, the power switching circuit 333 is an H-bridge 334which is shown in FIG. 8 and which is described in detail below. It is,however, to be appreciated that the bridge IC 301 of other examples mayincorporate an alternative power switching circuit to the H-bridge 334,provided that the power switching circuit performs an equivalentfunction for generating an AC drive signal to drive the ultrasonictransducer 215.

The bridge IC 301 comprises a first phase terminal PHASE A whichreceives a first phase output signal Phase A from the PWM signalgenerator subsystem of the PMIC 300. The bridge IC 301 also comprises asecond phase terminal PHASE B which receives a second phase outputsignal Phase B from the PWM signal generator subsystem of the PMIC 300.

The bridge IC 301 comprises a current sensing circuit 335 which sensescurrent flow in the H-bridge 334 directly and provides an RMS currentoutput signal via the RMS_CURR pin of the bridge IC 301. The currentsensing circuit 335 is configured for over current monitoring, to detectwhen the current flowing in the H-bridge 334 is above a predeterminedthreshold. The integration of the power switching circuit 333 comprisingthe H-bridge 334 and the current sensing circuit 335 all within the sameembedded circuit of the bridge IC 301 is a unique combination in the ICmarket. At present, no other integrated circuit in the IC marketcomprises an H-bridge with embedded circuitry for sensing the RMScurrent flowing through the H-bridge.

The bridge IC 301 comprises a temperature sensor 336 which includes overtemperature monitoring. The temperature sensor 336 is configured to shutdown the bridge IC 301 or disable at least part of the bridge IC 336 inthe event that the temperature sensor 336 detects that the bridge IC 301is operating at a temperature above a predetermined threshold. Thetemperature sensor 336 therefore provides an integrated safety functionwhich prevents damage to the bridge IC 301 or other components withinthe driver device 202 in the event that the bridge IC 301 operates at anexcessively high temperature.

The bridge IC 301 comprises a digital state machine 337 which isintegrally connected to the power switching circuit 333. The digitalstate machine 337 receives the phase A and phase B signals from the PMIC300 and an ENABLE signal, for instance from the microcontroller 303. Thedigital state machine 337 generates timing signals based on the firstphase output signal Phase A and the second phase output signal Phase B.

The digital state machine 337 outputs timing signals corresponding tothe phase A and phase B signals as well as a BRIDGE PR and BRIDGE ENsignals to the power switching circuit 333 in order to control the powerswitching circuit 333. The digital state machine 337 thus outputs thetiming signals to the switches T₁-T₄ of the H-bridge circuit 334 tocontrol the switches T₁-T₄ to turn on and off in a sequence such thatthe H-bridge circuit outputs an AC drive signal for driving a resonantcircuit, such as the ultrasonic transducer 215.

As described in more detail below, the switching sequence comprises afree-float period in which the first switch T₁ and the second switch T₁are turned off and the third switch T₃ and the fourth switch T₄ areturned on in order to dissipate energy stored by the resonant circuit(the ultrasonic transducer 215).

The bridge IC 301 comprises a test controller 338 which enables thebridge IC 301 to be tested to determine whether the embedded componentswithin the bridge IC 301 are operating correctly. The test controller338 is coupled to TEST_DATA, TEST_CLK and TEST_LOAD pins so that thebridge IC 301 can be connected to an external control device which feedsdata into and out from the bridge IC 301 to test the operation of thebridge IC 301. The bridge IC 301 also comprises a TEST BUS which enablesthe digital communication bus within the bridge IC 301 to be tested viaa TST_PAD pin.

The bridge IC 301 comprises a power on reset circuit (POR) 339 whichcontrols the startup operation of the bridge IC 301. The POR 339 ensuresthat the bridge IC 301 starts up properly only if the supply voltage iswithin a predetermined range. If the power supply voltage is outside ofthe predetermined range, for instance if the power supply voltage is toohigh, the POR 339 delays the startup of the bridge IC 301 until thesupply voltage is within the predetermined range.

The bridge IC 301 comprises a reference block (BG) 340 which provides aprecise reference voltage for use by the other subsystems of the bridgeIC 301.

The bridge IC 301 comprises a current reference 341 which provides aprecise current to the power switching circuit 333 and/or othersubsystems within the bridge IC 301, such as the current sensor 335.

The temperature sensor 336 monitors the temperature of the silicon ofthe bridge IC 301 continuously. If the temperature exceeds thepredetermined temperature threshold, the power switching circuit 333 isswitched off automatically. In addition, the over temperature may bereported to an external host to inform the external host that an overtemperature event has occurred.

The digital state machine (FSM) 337 generates the timing signals for thepower switching circuit 333 which, in this example, are timing signalsfor controlling the H-bridge 334.

The bridge IC 301 comprises comparators 342,343 which compare signalsfrom the various subsystems of the bridge IC 301 with the voltage andcurrent references 340,341 and provide reference output signals via thepins of the bridge IC 301.

Referring again to FIG. 8 of the accompanying drawings, the H-bridge 334of this example comprises four switches in the form of NMOS field effecttransistors (FET) switches on both sides of the H-bridge 334. TheH-bridge 334 comprises four switches or transistors T₁-T₄ which areconnected in an H-bridge configuration, with each transistor T₁-T₄ beingdriven by a respective logic input A-D. The transistors T₁-T₄ areconfigured to be driven by a bootstrap voltage which is generatedinternally with two external capacitors Cb which are connected asillustrated in FIG. 8 .

The H-bridge 334 comprises various power inputs and outputs which areconnected to the respective pins of the bridge IC 301. The H-bridge 334receives the programmable voltage VBOOST which is output from the boostconverter 305 via a first power supply terminal, labelled VBOOST in FIG.8 . The H-bridge 334 comprises a second power supply terminal, labelledVSS_P in FIG. 8 .

The H-bridge 334 comprises outputs OUTP, OUTN which are configured toconnect to respective terminals of the ultrasonic transducer 215 so thatthe AC drive signal output from the H-bridge 334 can drive theultrasonic transducer 215.

The switching of the four switches or transistors T₁-T₄ is controlled byswitching signals from the digital state machine 337 via the logic inputA-D. It is to be appreciated that, while FIG. 8 shows four transistorsT₁-T₄, in other examples, the H-bridge 334 incorporates a larger numberof transistors or other switching components to implement thefunctionality of the H-bridge.

In this example, the H-bridge 334 operates at a switching power of 22 Wto 50 W in order to deliver an AC drive signal with sufficient power todrive the ultrasonic transducer 215 optimally at or near the resonantfrequency of the ultrasonic transducer 215. The voltage which isswitched by the H-bridge 334 of this example is ±15 V. In otherexamples, the voltage is ±20 V.

In this example, the H-bridge 334 switches at a frequency of 3 MHz to 5MHz or up to 105 MHz. This is a high switching speed compared withconventional integrated circuit H-bridges which are available in the ICmarket. For instance, a conventional integrated circuit H-bridgeavailable in the IC market today is configured to operate at a maximumfrequency of only 2 MHz. Aside from the bridge IC 301 described herein,no conventional integrated circuit H-bridge available in the IC marketis able to operate at a power of 22 V to 50 V at a frequency of up to 5MHz, let alone up to 105 MHz.

Referring now to FIG. 9 of the accompanying drawings, the current sensor335 comprises positive and negative current sense resistors RshuntP,RshuntN which are connected in series with the respective high and lowsides of the H-bridge 334, as shown in FIG. 8 . The current senseresistors RshuntP, RshuntN are low value resistors which, in thisexample, are 0.1 Ω. The current sensor 335 comprises a first voltagesensor in the form of a first operational amplifier 344 which measuresthe voltage drop across the first current sensor resistor RshuntP and asecond voltage sensor in the form of a second operational amplifier 345which measures the voltage drop across the second current sensorresistor RshuntN. In this example, the gain of each operationalamplifier 344, 345 is 2 V/V. The output of each operational amplifier344, 345 is, in this example, 1 mA/V. The current sensor 335 comprises apull down resistor Rcs which, in this example, is 2 kΩ. The outputs ofthe operational amplifiers 344, 345 provide an output CSout which passesthrough a low pass filter 346 which removes transients in the signalCSout. An output Vout of the low pass filter 346 is the output signal ofthe current sensor 335.

The current sensor 335 thus measures the AC current flowing through theH-bridge 334 and respectively through the ultrasonic transducer 215. Thecurrent sensor 335 translates the AC current into an equivalent RMSoutput voltage (Vout) relative to ground. The current sensor 335 hashigh bandwidth capability since the H-bridge 334 can be operated at afrequency of up to 5 MHz or, in some examples, up to 105 MHz. The outputVout of the current sensor 335 reports a positive voltage which isequivalent to the measured AC rms current flowing through the ultrasonictransducer 215. The output voltage Vout of the current sensor 335 is, inthis example, fed back to the control circuitry within the bridge IC 301to enable the bridge IC 301 to shut down the H-bridge 334 in the eventthat the current flowing through the H-bridge 334 and hence through thetransducer 215 is in excess of a predetermined threshold. In addition,the over current threshold event is reported to the first comparator 342in the bridge IC 301 so that the bridge IC 301 can report the overcurrent event via the OVC_TRIGG pin of the bridge IC 301.

Referring now to FIG. 10 of the accompanying drawings, the control ofthe H-bridge 334 will now be described also with reference to theequivalent piezoelectric model of the ultrasonic transducer 215.

To develop a positive voltage across the outputs OUTP, OUTN of theH-bridge 334 as indicated by V_out in FIG. 10 (note the direction of thearrow) the switching sequence of the transistors T₁-T₄ via the inputsA-D is as follows:

-   -   1. Positive output voltage across the ultrasonic transducer 215:        A-ON, B-OFF, C-OFF, D-ON    -   2. Transition from positive output voltage to zero: A-OFF,        B-OFF, C-OFF, D-ON. During this transition, C is switched off        first to minimise or avoid power loss by minimising or avoiding        current flowing through A and C if there is a switching error or        delay in A.    -   3. Zero output voltage: A-OFF, B-OFF, C-ON, D-ON. During this        zero output voltage phase, the terminals of the outputs OUTP,        OUTN of the H-bridge 334 are grounded by the C and D switches        which remain on. This dissipates the energy stored by the        capacitors in the equivalent circuit of the ultrasonic        transducer, which minimises the voltage overshoot in the        switching waveform voltage which is applied to the ultrasonic        transducer.    -   4. Transition from zero to negative output voltage: A-OFF,        B-OFF, C-ON, D-OFF.    -   5. Negative output voltage across the ultrasonic transducer 215:        A-OFF, B-ON, C-ON, D-OFF

At high frequencies of up to 5 MHz or even up to 105 MHz, it will beappreciated that the time for each part of the switching sequence isvery short and in the order of nanoseconds or picoseconds. For instance,at a switching frequency of 6 MHz, each part of the switching sequenceoccurs in approximately 80 ns.

A graph showing the output voltage OUTP, OUTN of the H-bridge 334according to the above switching sequence is shown in FIG. 11 of theaccompanying drawings. The zero output voltage portion of the switchingsequence is included to accommodate for the energy stored by theultrasonic transducer 215 (e.g. the energy stored by the capacitors inthe equivalent circuit of the ultrasonic transducer). As describedabove, this minimises the voltage overshoot in the switching waveformvoltage which is applied to the ultrasonic transducer and henceminimises unnecessary power dissipation and heating in the ultrasonictransducer.

Minimising or removing voltage overshoot also reduces the risk of damageto transistors in the bridge IC 301 by preventing the transistors frombeing subject to voltages in excess of their rated voltage. Furthermore,the minimisation or removal of the voltage overshoot enables the bridgeIC 301 to drive the ultrasonic transducer accurately in a way whichminimises disruption to the current sense feedback loop describedherein. Consequently, the bridge IC 301 is able to drive the ultrasonictransducer at a high power of 22 W to 50 W or even as high as 70 W at ahigh frequency of up to 5 MHz or even up to 105 MHz.

The bridge IC 301 of this example is configured to be controlled by thePMIC 300 to operate in two different modes, referred to herein as aforced mode and a native frequency mode, These two modes of operationare novel over existing bridge ICs. In particular, the native frequencymode is a major innovation which offers substantial benefits in theaccuracy and efficiency of driving an ultrasonic transducer as comparedwith conventional devices.

Forced Frequency Mode (FFM)

In the forced frequency mode the H-bridge 334 is controlled in thesequence described above but at a user selectable frequency. As aconsequence, the H-bridge transistors T₁-T₄ are controlled in a forcedway irrespective of the inherent resonant frequency of the ultrasonictransducer 215 to switch the output voltage across the ultrasonictransducer 215. The forced frequency mode therefore allows the H-bridge334 to drive the ultrasonic transducer 215, which has a resonantfrequency f1, at different frequency f2.

Driving an ultrasonic transducer at a frequency which is different fromits resonant frequency may be appropriate in order to adapt theoperation to different applications. For example, it may be appropriateto drive an ultrasonic transducer at a frequency which is slightly offthe resonance frequency (for mechanical reasons to prevent mechanicaldamage to the transducer). Alternatively, it may be appropriate to drivean ultrasonic transducer at a low frequency but the ultrasonictransducer has, because of its size, a different native resonancefrequency.

The driver device 202 controls the bridge IC 301 to drive the ultrasonictransducer 215 in the forced frequency mode in response to theconfiguration of the driver device 202 for a particular application or aparticular ultrasonic transducer. For instance, the driver device 202may be configured to operate in the forced frequency mode when theresonant circuit device 201 is being used for a particular application,such as generating a mist from a liquid of a particular viscositycontaining a drug for delivery to a user.

Native Frequency Mode (NFM)

The following native frequency mode of operation is a significantdevelopment and provides benefits in improved accuracy and efficiencyover conventional ultrasonic drivers that are available on the IC markettoday.

The native frequency mode of operation follows the same switchingsequence as described above but the timing of the zero output portion ofthe sequence is adjusted to minimise or avoid problems that can occurdue to current spikes in the forced frequency mode operation. Thesecurrent spikes occur when the voltage across the ultrasonic transducer215 is switched to its opposite voltage polarity. An ultrasonictransducer which comprises a piezoelectric crystal has an electricalequivalent circuit which incorporates a parallel connected capacitor(e.g. see the piezo model in FIG. 10 ). If the voltage across theultrasonic transducer is hard-switched from a positive voltage to anegative voltage, due to the high dV/dt there can be a large currentflow current flow as the energy stored in the capacitor dissipates.

The native frequency mode avoids hard switching the voltage across theultrasonic transducer 215 from a positive voltage to a negative voltage(and vice versa). Instead, prior to applying the reversed voltage, theultrasonic transducer 215 (piezoelectric crystal) is left free-floatingwith zero voltage applied across its terminals for a free-float period.The PMIC 300 sets the drive frequency of the bridge IC 301 such that thebridge 334 sets the free-float period such that current flow inside theultrasonic transducer 215 (due to the energy stored within thepiezoelectric crystal) reverses the voltage across the terminals of theultrasonic transducer 215 during the free-float period.

Consequently, when the H-bridge 334 applies the negative voltage at theterminals of the ultrasonic transducer 215 the ultrasonic transducer 215(the capacitor in the equivalent circuit) has already been reversecharged and no current spikes occur because there is no high dV/dt.

It is, however, to be appreciated that it takes time for the chargewithin the ultrasonic transducer 215 (piezoelectric crystal) to build upwhen the ultrasonic transducer 215 is first activated. Therefore, theideal situation in which the energy within the ultrasonic transducer 215is to reverse the voltage during the free-float period occurs only afterthe oscillation inside the ultrasonic transducer 215 has built up thecharge. To accommodate for this, when the bridge IC 301 activates theultrasonic transducer 215 for the first time, the PMIC 300 controls thepower delivered through the H-bridge 334 to the ultrasonic transducer215 to a first value which is a low value (e.g. 5 V). The PMI 300 thencontrols the power delivered through the H-bridge 334 to the ultrasonictransducer 215 to increase over a period of time to a second value (e.g.15 V) which is higher than the first value in order to build up theenergy stored within the ultrasonic transducer 215. Current spikes stilloccur during this ramp of the oscillation until the current inside theultrasonic transducer 215 developed sufficiently. However, by using alow first voltage at start up those current spikes are kept sufficientlylow to minimise the impact on the operation of the ultrasonic transducer215.

In order to implement the native frequency mode, the driver device 202controls the frequency of the oscillator 315 and the duty cycle (ratioof turn-on time to free-float time) of the AC drive signal output fromthe H-bridge 334 with high precision. In this example, the driver device202 performs three control loops to regulate the oscillator frequencyand the duty cycle such that the voltage reversal at the terminals ofthe ultrasonic transducer 215 is as precise as possible and currentspikes are minimised or avoided as far as possible. The precise controlof the oscillator and the duty cycle using the control loops is asignificant advance in the field of IC ultrasonic drivers.

During the native frequency mode of operation, the current sensor 335senses the current flowing through the ultrasonic transducer 215(resonant circuit) during the free-float period. The digital statemachine 337 adapts the timing signals to switch on either the firstswitch T1 or the second switch T2 when the current sensor 335 sensesthat the current flowing through the ultrasonic transducer 215 (resonantcircuit) during the free-float period is zero.

FIG. 12 of the accompanying drawings shows the oscillator voltagewaveform 347 (V(osc)), a switching waveform 348 resulting from theturn-on and turn-off the left hand side high switch T1 of the H-bridge334 and a switching waveform 349 resulting from the turn-on and turn-offthe right hand side high switch T2 of the H-bridge 334. For anintervening free-float period 350, both high switches T1, T2 of theH-bridge 334 are turned off (free-floating phase). The duration of thefree-float period 350 is controlled by the magnitude of the free-floatcontrol voltage 351 (Vphioff).

FIG. 13 of the accompanying drawings shows the voltage waveform 352 at afirst terminal of the ultrasonic transducer 215 (the voltage waveform isreversed at the second terminal of the ultrasonic transducer 215) andthe piezo current 353 flowing through the ultrasonic transducer 215. Thepiezo current 353 represents an (almost) ideal sinusoidal waveform (thisis never possible in the forced frequency mode or in any bridge in theIC market).

Before the sinusoidal wave of the piezo current 353 reaches zero, theleft hand side high switch T1 of the H-bridge 334 is turned off (here,the switch T1 is turned off when the piezo current 353 is approximately6 A). The remaining piezo current 353 which flows within the ultrasonictransducer 215 due to the energy stored in the ultrasonic transducer 215(the capacitor of the piezo equivalent circuit) is responsible for thevoltage reversal during the free-float period 350. The piezo current 353decays to zero during the free-float period 350 and into negativecurrent flow domain thereafter. The terminal voltage at the ultrasonictransducer 215 drops from the supply voltage (in this case 19 V) to lessthan 2 V and the drop comes to a stop when the piezo current 353 reacheszero. This is the perfect time to turn on the low-side switch T3 of theH-bridge 334 in order to minimise or avoid a current spike.

Compared to the forced frequency mode described above, the nativefrequency mode has at least three advantages:

-   -   1. The current spike associated with hard switching of the        package capacitor is significantly reduced or avoided        completely.    -   2. Power loss due to hard switching is almost eliminated.    -   3. Frequency is regulated by the control loops and will be kept        close to the resonance of the piezo crystal (i.e. the native        resonance frequency of the piezo crystal).

In the case of the frequency regulation by the control loops (advantage3 above), the PMIC 300 starts by controlling the bridge IC 301 to drivethe ultrasonic transducer 215 at a frequency above the resonance of thepiezo crystal. The PMIC 300 then controls the bridge IC 301 to that thefrequency of the AC drive signal decays/reduces during start up. As soonas the frequency approaches resonance frequency of the piezo crystal,the piezo current will develop/increase rapidly. Once the piezo currentis high enough to cause the desired voltage reversal, the frequencydecay/reduction is stopped by the PMIC 300. The control loops of thePMIC 300 then take over the regulation of frequency and duty cycle ofthe AC drive signal.

In the forced frequency mode, the power delivered to the ultrasonictransducer 215 is controlled through the duty cycle and/or a frequencyshift and/or by varying the supply voltage. However, in this example inthe native frequency mode the power delivered to the ultrasonictransducer 215 controlled only through the supply voltage.

In this example, during a setup phase of operation of the driver device,the bridge IC 301 is configured to measure the length of time taken forthe current flowing through the ultrasonic transducer 215 (resonantcircuit) to fall to zero when the first switch T₁ and the second switchT₂ are turned off and the third switch T₃ and the fourth switch T₄ areturned on. The bridge IC 301 then sets the length of time of thefree-float period to be equal to the measured length of time.

Referring now to FIG. 14 of the accompanying drawings, the PMIC 300 andthe bridge IC 301 of this example are designed to work together as acompanion chip set. The PMIC 300 and the bridge IC 301 are connectedtogether electrically for communication with one another. In thisexample, there are interconnections between the PMIC 300 and the bridgeIC 301 which enable the following two categories of communication:

-   -   1. control signals    -   2. feedback signals

The connections between the PHASE _A and PHASE_B pins of the PMIC 300and the bridge IC 301 carry the PWM modulated control signals whichdrive the H-bridge 334. The connection between the EN_BR pins of thePMIC 300 and the bridge IC 301 carries the EN_BR control signal whichtriggers the start of the H-bridge 334. The timing between the PHASE_A,PHASE_B and EN_BR control signals is important and handled by thedigital bridge control of the PMIC 300.

The connections between the CS, OC and OT pins of the PMIC 300 and thebridge IC 301 carry CS (current sense), OC (over current) and OT (overtemperature) feedback signals from the bridge IC 301 back to the PMIC300. Most notably, the CS (current sense) feedback signal comprises avoltage equivalent to the rms current flowing through the ultrasonictransducer 215 which is measured by the current sensor 335 of the bridgeIC 301.

The OC (over current) and OT (over temperature) feedback signals aredigital signals indicating that either an over current or an overvoltage event has been detected by the bridge IC 301. In this example,the thresholds for the over current and over temperature are set with anexternal resistor. Alternatively, the thresholds can also be dynamicallyset in response to signals passed to the OC_REF pin of the bridge IC 301from one of the two DAC channels VDAC0, VDAC1 from the PMIC 300.

In this example, the design of the PMIC 300 and the bridge IC 301 allowthe pins of these two integrated circuits to be connected directly toone another (e.g. via copper tracks on a PCB) so that there is minimalor no lag in the communication of signals between the PMIC 300 and thebridge IC 301. This provides a significant speed advantage overconventional bridges in the IC market which are typically controlled bysignals via a digital communications bus. For example, a standard I2Cbus is clocked at only 400 kHz, which is too slow for communicating datasampled at the high clock speeds of up to 5 MHz of examples of thisdisclosure.

While examples of this disclosure have been described above in relationto the microchip hardware, it is to be appreciated that other examplesof this disclosure comprise a method of operating the components andsubsystems of each microchip to perform the functions described herein.For instance, the methods of operating the PMIC 300 and the bridge IC301 in either the forced frequency mode or the native frequency mode.

Referring now to FIG. 15 of the accompanying drawings, the optional OTPIC 242 comprises a power on reset circuit (POR) 354, a bandgap reference(BG) 355, a cap-less low dropout regulator (LDO) 356, a communication(e.g. I2C) interface 357, a one-time programmable memory bank (eFuse)358, an oscillator 359 and a general purpose input-output interface 360.The OTP IC 242 also comprises a digital core 361 which includes acryptographic authenticator. In this example, the cryptographicauthenticator uses the Elliptic Curve Digital Signature Algorithm(ECDSA) for encrypting/decrypting data stored within the OTP IC 242 aswell as data transmitted to and from the OTP IC 242.

The POR 354 ensures that the OTP IC 242 starts up properly only if thesupply voltage is within a predetermined range. If the supply voltage isoutside the predetermined range, the POR 354 resets the OTP IC 242 andwaits until the supply voltage is within the predetermined range.

The BG 355 provides precise reference voltages and currents to the LDO356 and to the oscillator 359. The LDO 356 supplies the digital core361, the communication interface 357 and the eFuse memory bank 358.

The OTP IC 242 is configured to operate in at least the following modes:

-   -   Fuse Programming (Fusing): During efuse programming (programming        of the one time programmable memory) a high current is required        to burn the relevant fuses within the eFuse memory bank 358. In        this mode higher bias currents are provided to maintain gain and        bandwidth of the regulation loop.    -   Fuse Reading: In this mode a medium level current is required to        maintain efuse reading within the eFuse memory bank 358. This        mode is executed during the startup of the OTP IC 242 to        transfer the content of the fuses to shadow registers. In this        mode the gain and bandwidth of the regulation loop is set to a        lower value than in the Fusing Mode.    -   Normal Operation: In this mode the LDO 356 is driven in a very        low bias current condition to operate the OTP IC 242 with low        power so that the OTP IC 242 consumes as little power as        possible.

The oscillator 359 provides the required clock for the digitalcore/engine 361 during testing (SCAN Test), during fusing and duringnormal operation. The oscillator 359 is trimmed to cope with the stricttiming requirements during the fusing mode.

In this example, the communication interface 357 is compliant with theFM+ specification of the I2C standard but it also complies with slow andfast mode. The OTP IC 242 uses the communication interface 357 tocommunicate with the driver device 202 (the Host) for data and keyexchange.

The digital core 361 implements the control and communicationfunctionality of the OTP IC 242. The cryptographic authenticator of thedigital core 361 enables the OTP IC 242 to authenticate itself (e.g.using ECDSA encrypted messages) with the driver device 202 (e.g. for aparticular application) to ensure that the OTP IC 242 is genuine andthat the OTP IC 242 is authorised to connect to the driver device 202(or another product).

With reference to FIG. 16 of the accompanying drawings, the OTP IC 242performs the following PKI procedure in order to authenticate the OTP IC242 for use with a Host (e.g. the driver device 202):

-   -   1. Verify Signer Public Key: The Host requests the Manufacturing        Public key and Certificate. The Host verifies the certificate        with the Authority Public key.    -   2. Verify Device Public Key: If the verification is successful,        the Host requests the Device Public key and Certificate. The        Host verifies the certificate with the Manufacturing Public key.    -   3. Challenge—Response: If the verification is successful, the        Host creates a random number challenge and sends it to the        Device. The End Product signs the random number challenge with        the Device Private key.    -   4. The signature is sent back to the Host for verification using        the Device Public key.

If all steps of the authentication procedure complete successfully thenthe Chain of Trust has been verified back to the Root of Trust and theOTP IC 242 is successfully authenticated for use with the Host. However,if any of the steps of the authentication procedure fail then the OTP IC242 is not authenticated for use with the Host and use of the deviceincorporating the OTP IC 242 is restricted or prevented.

The foregoing outlines features of several examples or embodiments sothat those of ordinary skill in the art may better understand variousaspects of the present disclosure. Those of ordinary skill in the artshould appreciate that they may readily use the present disclosure as abasis for designing or modifying other processes and structures forcarrying out the same purposes and/or achieving the same advantages ofvarious examples or embodiments introduced herein. Those of ordinaryskill in the art should also realise that such equivalent constructionsdo not depart from the spirit and scope of the present disclosure, andthat they may make various changes, substitutions, and alterationsherein without departing from the spirit and scope of the presentdisclosure.

Although the subject matter has been described in language specific tostructural features or methodological acts, it is to be understood thatthe subject matter of the appended claims is not necessarily limited tothe specific features or acts described above. Rather, the specificfeatures and acts described above are disclosed as example forms ofimplementing at least some of the claims.

Various operations of examples or embodiments are provided herein. Theorder in which some or all of the operations are described should not beconstrued to imply that these operations are necessarily orderdependent. Alternative ordering will be appreciated having the benefitof this description. Further, it will be understood that not alloperations are necessarily present in each embodiment provided herein.Also, it will be understood that not all operations are necessary insome examples or embodiments.

Moreover, “exemplary” is used herein to mean serving as an example,instance, illustration, etc., and not necessarily as advantageous. Asused in this application, “or” is intended to mean an inclusive “or”rather than an exclusive “or”. In addition, “a” and “an” as used in thisapplication and the appended claims are generally be construed to mean“one or more” unless specified otherwise or clear from context to bedirected to a singular form. Also, at least one of A and B and/or thelike generally means A or B or both A and B. Furthermore, to the extentthat “includes”, “having”, “has”, “with”, or variants thereof are used,such terms are intended to be inclusive in a manner similar to the term“comprising”. Also, unless specified otherwise, “first,” “second,” orthe like are not intended to imply a temporal aspect, a spatial aspect,an ordering, etc. Rather, such terms are merely used as identifiers,names, etc. for features, elements, items, etc. For example, a firstelement and a second element generally correspond to element A andelement B or two different or two identical elements or the sameelement.

Also, although the disclosure has been shown and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others of ordinary skill in the art based upon a readingand understanding of this specification and the annexed drawings. Thedisclosure comprises all such modifications and alterations and islimited only by the scope of the following claims. In particular regardto the various functions performed by the above described features(e.g., elements, resources, etc.), the terms used to describe suchfeatures are intended to correspond, unless otherwise indicated, to anyfeatures which performs the specified function of the described features(e.g., that is functionally equivalent), even though not structurallyequivalent to the disclosed structure. In addition, while a particularfeature of the disclosure may have been disclosed with respect to onlyone of several implementations, such feature may be combined with one ormore other features of the other implementations as may be desired andadvantageous for any given or particular application.

Examples or embodiments of the subject matter and the functionaloperations described herein can be implemented in digital electroniccircuitry, or in computer software, firmware, or hardware, including thestructures disclosed in this specification and their structuralequivalents, or in combinations of one or more of them.

Some examples or embodiments are implemented using one or more modulesof computer program instructions encoded on a computer-readable mediumfor execution by, or to control the operation of, a data processingapparatus. The computer-readable medium can be a manufactured product,such as hard drive in a computer system or an embedded system. Thecomputer-readable medium can be acquired separately and later encodedwith the one or more modules of computer program instructions, such asby delivery of the one or more modules of computer program instructionsover a wired or wireless network. The computer-readable medium can be amachine-readable storage device, a machine-readable storage substrate, amemory device, or a combination of one or more of them.

The terms “computing device” and “data processing apparatus” encompassall apparatus, devices, and machines for processing data, including byway of example a programmable processor, a computer, or multipleprocessors or computers. The apparatus can include, in addition tohardware, code that creates an execution environment for the computerprogram in question, e.g., code that constitutes processor firmware, aprotocol stack, a database management system, an operating system, aruntime environment, or a combination of one or more of them. Inaddition, the apparatus can employ various different computing modelinfrastructures, such as web services, distributed computing and gridcomputing infrastructures.

The processes and logic flows described in this specification can beperformed by one or more programmable processors executing one or morecomputer programs to perform functions by operating on input data andgenerating output.

Processors suitable for the execution of a computer program include, byway of example, both general and special purpose microprocessors, andany one or more processors of any kind of digital computer. Generally, aprocessor will receive instructions and data from a read-only memory ora random access memory or both. The essential elements of a computer area processor for performing instructions and one or more memory devicesfor storing instructions and data. Generally, a computer will alsoinclude, or be operatively coupled to receive data from or transfer datato, or both, one or more mass storage devices for storing data, e.g.,magnetic, magneto-optical disks, or optical disks. However, a computerneed not have such devices. Devices suitable for storing computerprogram instructions and data include all forms of non-volatile memory,media and memory devices.

When used in this specification and claims, the terms “comprises” and“comprising” and variations thereof mean that the specified features,steps or integers are included. The terms are not to be interpreted toexclude the presence of other features, steps or components.

The invention may also broadly consist in the parts, elements, steps,examples and/or features referred to or indicated in the specificationindividually or collectively in any and all combinations of two or moresaid parts, elements, steps, examples and/or features. In particular,one or more features in any of the embodiments described herein may becombined with one or more features from any other embodiment(s)described herein.

Protection may be sought for any features disclosed in any one or morepublished documents referenced herein in combination with the presentdisclosure.

REPRESENTATIVE FEATURES

Representative features are set out in the following clauses, whichstand alone or may be combined, in any combination, with one or morefeatures disclosed in the text and/or drawings of the specification.

-   -   1. A microchip for driving a resonant circuit, wherein the        resonant circuit is an LC tank, an antenna or a piezoelectric        transducer, and wherein the microchip is a single unit which        comprises a plurality of interconnected embedded components and        subsystems comprising;        -   an oscillator which generates:            -   a main clock signal,            -   a first phase clock signal which is high for a first                time during the positive half-period of the main clock                signal and low during the negative haft-period of the                main clock signal, and            -   a second phase clock signal which is high for a second                time during the negative half-period of the main clock                signal and low during the positive half-period of the                main clock signal, wherein the phases of the first phase                clock signal and the second phase clock signal are                centre aligned;        -   a pulse width modulation (PWM) signal generator subsystem            comprising:            -   a delay locked loop which generates a double frequency                clock signal using the first phase clock signal and the                second phase clock signal, the double frequency clock                signal being double the frequency of the main clock                signal, wherein the delay locked loop controls the                rising edge of the first phase clock signal and the                second phase clock signal to be synchronous with the                rising edge of the double frequency clock signal, and                wherein the delay locked loop adjusts the frequency and                the duty cycle of the first phase clock signal and the                second phase clock signal in response to a driver                control signal to produce a first phase output signal                and a second phase output signal, wherein the first                phase output signal and the second phase output signal                are configured to drive an H-bridge circuit to generate                an AC drive signal to drive the resonant circuit;            -   a first phase output signal terminal which outputs the                first phase output signal to the H-bridge circuit;            -   a second phase output signal terminal which outputs the                second phase output signal to the H-bridge circuit;            -   a feedback input terminal which receives a feedback                signal from the H-bridge circuit;        -   an analogue to digital converter (ADC) subsystem comprising:            -   a plurality of ADC input terminals which receive a                plurality of respective analogue signals, wherein one                ADC input terminal of the plurality of ADC input                terminals is connected to the feedback input terminal                such that the ADC subsystem receives the feedback signal                from the H-bridge circuit, and wherein the ADC subsystem                samples analogue signals received at the plurality of                ADC input terminals at a sampling frequency which is                proportional to the frequency of the main clock signal                and the ADC subsystem generates ADC digital signals                using the sampled analogue signals;        -   a digital processor subsystem which receives the ADC digital            signals from the ADC subsystem and processes the ADC digital            signals to generate the driver control signal, wherein the            digital processor subsystem communicates the driver control            signal to the PWM signal generator subsystem to control the            PWM signal generator subsystem; and        -   a digital to analogue converter (DAC) subsystem comprising:            -   a digital to analogue converter (DAC) which converts a                digital control signal generated by the digital                processor subsystem into an analogue voltage control                signal to control a voltage regulator circuit which                generates a voltage for modulation by the H-bridge                circuit; and            -   a DAC output terminal which outputs the analogue voltage                control signal to control the voltage regulator circuit                to generate a predetermined voltage for modulation by                the H-bridge circuit to drive the resonant circuit in                response to feedback signals which are indicative of the                operation of the resonant circuit.    -   2. The microchip of clause 1, wherein the oscillator generates        the main clock signal at a frequency of 50 kHz to 105 MHz.    -   3. The microchip of clause 1, wherein the microchip further        comprises:        -   a frequency divider which is connected to the oscillator to            receive the main clock signal from the oscillator, the            frequency divider dividing the main clock signal by a            predetermined divisor amount and outputting the frequency            reference signal to the delay locked loop.    -   4. The microchip of clause 1, wherein the delay locked loop        comprises a plurality of delay lines connected end to end,        wherein the total delay of the delay lines is equal to the        period of the main clock signal.    -   5. The microchip of clause 4, wherein the delay locked loop        adjusts the duty cycle of the first phase clock signal and the        second phase clock signal in response to the driver control        signal by varying the delay of each delay line in the delay        locked loop.    -   6. The microchip of clause 1, wherein the feedback input        terminal receives a feedback signal which is indicative of a        parameter of the operation of the H-bridge circuit or AC drive        signal when the H-bridge circuit is driving the resonant circuit        with the AC drive signal.    -   7. The microchip of clause 1, wherein the feedback input        terminal receives a feedback signal from the H-bridge circuit in        the form of a voltage which indicative of an rms current of an        AC drive signal which is driving the resonant circuit.    -   8. The microchip of clause 1, wherein the ADC subsystem        comprises a plurality of further ADC input terminals which        receive feedback signals which are indicative of at least one of        the voltage of a battery connected to the microchip or the        voltage of a battery charger connected to the microchip.    -   9. The microchip of clause 1, wherein the microchip further        comprises:        -   a temperature sensor which is embedded within the microchip,            wherein the temperature sensor generates a temperature            signal which is indicative of the temperature of the            microchip, and wherein the temperature signal is received by            a further ADC input terminal of the ADC subsystem and the            temperature signal is sampled by the ADC.    -   10. The microchip of clause 1, wherein the ADC subsystem samples        signals received at the plurality of ADC input terminals        sequentially with each signal being sampled by the ADC subsystem        a respective predetermined number of times.    -   11. The microchip of clause 1, wherein the microchip further        comprises:        -   a battery charging subsystem which controls the charging of            an external battery which is connected to the microchip.    -   12. The microchip of clause 1, wherein the DAC subsystem        comprises: a further digital to analogue converter (DAC) which        converts a further digital control signal generated by the        digital processor subsystem into a further analogue voltage        control signal to control the voltage regulator circuit.    -   13. A microchip for driving a resonant circuit, wherein the        resonant circuit is an LC tank, an antenna or a piezoelectric        transducer, and wherein the microchip is a single unit which        comprises a plurality of interconnected embedded components and        subsystems comprising:        -   a first power supply terminal;        -   a second power supply terminal;        -   an H-bridge circuit which incorporates a first switch, a            second switch, a third switch and a fourth switch, wherein:            -   the first switch and the third switch are connected in                series between the first power supply terminal and the                second power supply terminal;            -   a first output terminal is connected electrically                between the first switch and the third switch,            -   the second switch and the fourth switch are connected in                series between the first power supply terminal and the                second power supply terminal, and            -   a second output terminal is connected electrically                between the second switch and the fourth switch;        -   a first phase terminal which receives a first phase output            signal from a pulse width modulation (PWM) signal generator;        -   a second phase terminal which receives a second phase output            signal from the PWM signal generator;        -   a digital state machine which generates timing signals based            on the first phase output signal and the second phase output            signal and outputs the timing signals to the switches of the            H-bridge circuit to control the switches to turn on and off            in a sequence such that the H-bridge circuit outputs an AC            drive signal for driving the resonant circuit, wherein the            sequence comprises a free-float period in which the first            switch and the second switch are turned off and the third            switch and the fourth switch are turned on in order to            dissipate energy stored by the resonant circuit;        -   a current sensor which incorporates:            -   a first current sense resistor which is connected in                series between the first switch and the first power                supply terminal;            -   a first voltage sensor which measures the voltage drop                across the first current sense resistor and provides a                first voltage output which is indicative of the current                flowing through the first current sense resistor;            -   a second current sense resistor which is connected in                series between the second switch and the first power                supply terminal;            -   a second voltage sensor which measures the voltage drop                across the second current sensor resistor and provides a                second voltage output which is indicative of the current                flowing through the second current sense resistor; and            -   a current sensor output terminal which provides an rms                output voltage relative to ground which is equivalent to                the first voltage output and the second voltage output,                wherein the rms output voltage is indicative of an rms                current flowing through the first switch or the second                switch and the current flowing through the resonant                circuit which is connected between the first output                terminal and the second output terminal.    -   14. The microchip of clause 13, wherein the H-bridge circuit is        configured to output a power of 22 W to 50 W to the resonant        circuit which is connected to the first output terminal and the        second output terminal.    -   15. The microchip of clause 13, wherein the microchip further        comprises:        -   a temperature sensor which is embedded within the microchip,            wherein the temperatures sensor measures the temperature of            the microchip and disables at least part of the microchip in            the event that the temperature sensor senses that the            microchip is at a temperature which is in excess of a            predetermined threshold.    -   16. An apparatus for driving a resonant circuit, wherein the        resonant circuit is an LC tank, an antenna or a piezoelectric        transducer, the apparatus comprising:        -   a first microchip, wherein the first microchip is a single            unit which comprises a plurality of interconnected embedded            components and subsystems comprising:        -   a first power supply terminal;        -   a second power supply terminal;        -   an H-bridge circuit which incorporates a first switch, a            second switch, a third switch and a fourth switch, wherein:            -   the first switch and the third switch are connected in                series between the first power supply terminal and the                second power supply terminal;            -   a first output terminal is connected electrically                between the first switch and the third switch,            -   the second switch and the fourth switch are connected in                series between the first power supply terminal and the                second power supply terminal, and            -   a second output terminal is connected electrically                between the second switch and the fourth switch;        -   a first phase terminal which receives a first phase output            signal from a pulse width modulation (PWM) signal generator            subsystem;        -   a second phase terminal which receives a second phase output            signal from the PWM signal generator;        -   a digital state machine which generates timing signals based            on the first phase output signal and the second phase output            signal and outputs the timing signals to the switches of the            H-bridge circuit to control the switches to turn on and off            in a sequence such that the H-bridge circuit outputs an AC            drive signal to the resonant circuit to drive the resonant            circuit to generate and transmit the ultrasonic waves,            wherein the sequence comprises a free-float period in which            the first switch and the second switch are turned off and            the third switch and the fourth switch are turned on in            order to dissipate energy stored by the resonant circuit;        -   a current sensor which incorporates:            -   a first current sense resistor which is connected in                series between the first switch and the first power                supply terminal;            -   a first voltage sensor which measures the voltage drop                across the first current sense resistor and provides a                first voltage output which is indicative of the current                flowing through the first current sense resistor;            -   a second current sense resistor which is connected in                series between the second switch and the first power                supply terminal;            -   a second voltage sensor which measures the voltage drop                across the second current sensor resistor and provides a                second voltage output which is indicative of the current                flowing through the second current sense resistor; and            -   a current sensor output terminal which provides an rms                output voltage relative to ground which is equivalent to                the first voltage output and the second voltage output,        -   wherein the rms output voltage is indicative of an rms            current flowing through the first switch or the second            switch and the current flowing through the resonant circuit            which is connected between the first output terminal and the            second output terminal; and        -   a second microchip connected to the first microchip to            control the H-bridge circuit to generate the AC drive            signal, wherein the second microchip is a single unit which            comprises a plurality of interconnected embedded components            and subsystems comprising:        -   an oscillator which generates:            -   a main clock signal,        -   a first phase clock signal which is high for a first time            during the positive half-period of the main clock signal and            low during the negative half-period of the main clock            signal, and            -   a second phase clock signal which is high for a second                time during the negative half-period of the main clock                signal and low during the positive half-period of the                main clock signal, wherein the phases of the first phase                clock signal and the second phase clock signal are                centre aligned;        -   the pulse width modulation PWM signal generator subsystem,            wherein the PWM signal generator subsystem comprises:            -   a delay locked loop which generates a double frequency                clock signal using the first phase clock signal and the                second phase clock signal, the double frequency clock                signal being double the frequency of the main clock                signal, wherein the delay locked loop controls the                rising edge of the first phase clock signal and the                second phase clock signal to be synchronous with the                rising edge of the double frequency clock signal, and                wherein the delay locked loop adjusts the frequency and                the duty cycle of the first phase clock signal and the                second phase clock signal in response to a driver                control signal to produce a first phase output signal                and a second phase output signal, wherein the first                phase output signal and the second phase output signal                are configured to drive the H-bridge circuit to generate                an AC drive signal to drive the resonant circuit;            -   a first phase output signal terminal which outputs the                first phase output signal to the H-bridge circuit;            -   a second phase output signal terminal which outputs the                second phase output signal to the H-bridge circuit;            -   a feedback input terminal which receives a feedback                signal from the H-bridge circuit, the feedback signal                being indicative of a parameter of the operation of the                H-bridge circuit or the AC drive signal when the                H-bridge circuit is driving the resonant circuit with                the AC drive signal;        -   an analogue to digital converter (ADC) subsystem comprising:            -   a plurality of ADC input terminals which receive a                plurality of respective analogue signals, wherein one                ADC input terminal of the plurality of ADC input                terminals is connected to the feedback input terminal                such that the ADC subsystem receives the feedback signal                from the H-bridge circuit, and wherein the ADC subsystem                samples analogue signals received at the plurality of                ADC input terminals at a sampling frequency which is                proportional to the frequency of the main clock signal                and the ADC subsystem generates ADC digital signals                using the sampled analogue signals;        -   a digital processor subsystem which receives the ADC digital            signals from the ADC subsystem and processes the ADC digital            signals to generate the driver control signal, wherein the            digital processor subsystem communicates the driver control            signal to the PWM signal generator subsystem to control the            PWM signal generator subsystem; and        -   a digital to analogue converter (DAC) subsystem comprising:            -   a digital to analogue converter (DAC) which converts a                digital control signal generated by the digital                processor subsystem into an analogue voltage control                signal to control a voltage regulator circuit which                generates a voltage for modulation by the H-bridge                circuit; and    -   a DAC output terminal which outputs the analogue voltage control        signal to control the voltage regulator circuit to generate a        predetermined voltage for modulation by the H-bridge circuit to        drive the resonant circuit in response to feedback signals which        are indicative of the operation of the resonant circuit.    -   17. The apparatus of clause 16, wherein the apparatus further        comprises:        -   a boost converter circuit which is configured to increase            the voltage of a power supply to a boost voltage in response            to the analogue voltage output signal from the DAC output            terminal, wherein the boost converter circuit provides the            boost voltage at the first power supply terminal such that            the boost voltage is modulated by the switching of the            switches of the H-bridge circuit.    -   18. The apparatus of clause 16, wherein the current sensor        senses the current flowing through the resonant circuit during        the free-float period and the digital state machine adapts the        timing signals to switch on either the first switch or the        second switch when the current sensor senses that the current        flowing through the resonant circuit during the free-float        period is zero.    -   19. The apparatus of clause 16, wherein, during a setup phase of        operation of the apparatus, the second microchip:        -   measures the length of time taken for the current flowing            through the resonant circuit to fall to zero when the first            switch and the second switch are turned off and the third            switch and the fourth switch are turned on; and        -   sets the length of time of the free-float period to be equal            to the measured length of time.

Although certain example embodiments of the invention have beendescribed, the scope of the appended claims is not intended to belimited solely to these embodiments. The claims are to be construedliterally, purposively, and/or to encompass equivalents.

1. A microchip for driving a resonant circuit, wherein the resonantcircuit is an LC tank, an antenna or a piezoelectric transducer, andwherein the microchip is a single unit which comprises a plurality ofinterconnected embedded components and subsystems comprising: anoscillator which generates: a main clock signal, a first phase clocksignal which is high for a first time during the positive half-period ofthe main clock signal and low during the negative half-period of themain clock signal, and a second phase clock signal which is high for asecond time during the negative half-period of the main clock signal andlow during the positive half-period of the main clock signal, whereinthe phases of the first phase clock signal and the second phase clocksignal are centre aligned; a pulse width modulation (PWM) signalgenerator subsystem comprising: a delay locked loop which generates adouble frequency clock signal using the first phase clock signal and thesecond phase clock signal, the double frequency clock signal beingdouble the frequency of the main clock signal, wherein the delay lockedloop controls the rising edge of the first phase clock signal and thesecond phase clock signal to be synchronous with the rising edge of thedouble frequency clock signal, and wherein the delay locked loop adjuststhe frequency and the duty cycle of the first phase clock signal and thesecond phase clock signal in response to a driver control signal toproduce a first phase output signal and a second phase output signal,wherein the first phase output signal and the second phase output signalare configured to drive an H-bridge circuit to generate an AC drivesignal to drive the resonant circuit; a first phase output signalterminal which outputs the first phase output signal to the H-bridgecircuit; a second phase output signal terminal which outputs the secondphase output signal to the H-bridge circuit; a feedback input terminalwhich receives a feedback signal from the H-bridge circuit; an analogueto digital converter (ADC) subsystem comprising: a plurality of ADCinput terminals which receive a plurality of respective analoguesignals, wherein one ADC input terminal of the plurality of ADC inputterminals is connected to the feedback input terminal such that the ADCsubsystem receives the feedback signal from the H-bridge circuit, andwherein the ADC subsystem samples analogue signals received at theplurality of ADC input terminals at a sampling frequency which isproportional to the frequency of the main clock signal and the ADCsubsystem generates ADC digital signals using the sampled analoguesignals; a digital processor subsystem which receives the ADC digitalsignals from the ADC subsystem and processes the ADC digital signals togenerate the driver control signal, wherein the digital processorsubsystem communicates the driver control signal to the PWM signalgenerator subsystem to control the PWM signal generator subsystem; and adigital to analogue converter (DAC) subsystem comprising: a digital toanalogue converter (DAC) which converts a digital control signalgenerated by the digital processor subsystem into an analogue voltagecontrol signal to control a voltage regulator circuit which generates avoltage for modulation by the H-bridge circuit; and a DAC outputterminal which outputs the analogue voltage control signal to controlthe voltage regulator circuit to generate a predetermined voltage formodulation by the H-bridge circuit to drive the resonant circuit inresponse to feedback signals which are indicative of the operation ofthe resonant circuit.
 2. The microchip of claim 1, wherein theoscillator generates the main clock signal at a frequency of 50 kHz to105 MHz.
 3. The microchip of claim 1, wherein the microchip furthercomprises: a frequency divider which is connected to the oscillator toreceive the main clock signal from the oscillator, the frequency dividerdividing the main clock signal by a predetermined divisor amount andoutputting the frequency reference signal to the delay locked loop. 4.The microchip of claim 1, wherein the delay locked loop comprises aplurality of delay lines connected end to end, wherein the total delayof the delay lines is equal to the period of the main clock signal. 5.The microchip of claim 4, wherein the delay locked loop adjusts the dutycycle of the first phase clock signal and the second phase clock signalin response to the driver control signal by varying the delay of eachdelay line in the delay locked loop.
 6. The microchip of claim 1,wherein the feedback input terminal receives a feedback signal which isindicative of a parameter of the operation of the H-bridge circuit or ACdrive signal when the H-bridge circuit is driving the resonant circuitwith the AC drive signal.
 7. The microchip of claim 1, wherein thefeedback input terminal receives a feedback signal from the H-bridgecircuit in the form of a voltage which indicative of an rms current ofan AC drive signal which is driving the resonant circuit.
 8. Themicrochip of claim 1, wherein the ADC subsystem comprises a plurality offurther ADC input terminals which receive feedback signals which areindicative of at least one of the voltage of a battery connected to themicrochip or the voltage of a battery charger connected to themicrochip.
 9. The microchip of claim 1, wherein the microchip furthercomprises: a temperature sensor which is embedded within the microchip,wherein the temperature sensor generates a temperature signal which isindicative of the temperature of the microchip, and wherein thetemperature signal is received by a further ADC input terminal of theADC subsystem and the temperature signal is sampled by the ADC.
 10. Themicrochip of claim 1, wherein the ADC subsystem samples signals receivedat the plurality of ADC input terminals sequentially with each signalbeing sampled by the ADC subsystem a respective predetermined number oftimes.
 11. The microchip of claim 1, wherein the microchip furthercomprises: a battery charging subsystem which controls the charging ofan external battery which is connected to the microchip.
 12. Themicrochip of claim 1, wherein the DAC subsystem comprises: a furtherdigital to analogue converter (DAC) which converts a further digitalcontrol signal generated by the digital processor subsystem into afurther analogue voltage control signal to control the voltage regulatorcircuit.
 13. A microchip for driving a resonant circuit, wherein theresonant circuit is an LC tank, an antenna or a piezoelectrictransducer, and wherein the microchip is a single unit which comprises aplurality of interconnected embedded components and subsystemscomprising: a first power supply terminal; a second power supplyterminal; an H-bridge circuit which incorporates a first switch, asecond switch, a third switch and a fourth switch, wherein: the firstswitch and the third switch are connected in series between the firstpower supply terminal and the second power supply terminal; a firstoutput terminal is connected electrically between the first switch andthe third switch, the second switch and the fourth switch are connectedin series between the first power supply terminal and the second powersupply terminal, and a second output terminal is connected electricallybetween the second switch and the fourth switch; a first phase terminalwhich receives a first phase output signal from a pulse width modulation(PWM) signal generator; a second phase terminal which receives a secondphase output signal from the PWM signal generator; a digital statemachine which generates timing signals based on the first phase outputsignal and the second phase output signal and outputs the timing signalsto the switches of the H-bridge circuit to control the switches to turnon and off in a sequence such that the H-bridge circuit outputs an ACdrive signal for driving the resonant circuit, wherein the sequencecomprises a free-float period in which the first switch and the secondswitch are turned off and the third switch and the fourth switch areturned on in order to dissipate energy stored by the resonant circuit, acurrent sensor which incorporates: a first current sense resistor whichis connected in series between the first switch and the first powersupply terminal; a first voltage sensor which measures the voltage dropacross the first current sense resistor and provides a first voltageoutput which is indicative of the current flowing through the firstcurrent sense resistor; a second current sense resistor which isconnected in series between the second switch and the first power supplyterminal; a second voltage sensor which measures the voltage drop acrossthe second current sensor resistor and provides a second voltage outputwhich is indicative of the current flowing through the second currentsense resistor; and a current sensor output terminal which provides anrms output voltage relative to around which is equivalent to the firstvoltage output and the second voltage output, wherein the rms outputvoltage is indicative of an rms current flowing through the first switchor the second switch and the current flowing through the resonantcircuit which is connected between the first output terminal and thesecond output terminal.
 14. The microchip of claim 13, wherein theH-bridge circuit is configured to output a power of 22 W to 50 W to theresonant circuit which is connected to the first output terminal and thesecond output terminal.
 15. The microchip of claim 13, wherein themicrochip further comprises: a temperature sensor which is embeddedwithin the microchip, wherein the temperatures sensor measures thetemperature of the microchip and disables at least part of the microchipin the event that the temperature sensor senses that the microchip is ata temperature which is in excess of a predetermined threshold.
 16. Anapparatus for driving a resonant circuit, wherein the resonant circuitis an LC tank, an antenna or a piezoelectric transducer, the apparatuscomprising: a first microchip, wherein the first microchip is a singleunit which comprises a plurality of interconnected embedded componentsand subsystems comprising: a first power supply terminal; a second powersupply terminal; an H-bridge circuit which incorporates a first switch,a second switch, a third switch and a fourth switch, wherein: the firstswitch and the third switch are connected in series between the firstpower supply terminal and the second power supply terminal; a firstoutput terminal is connected electrically between the first switch andthe third switch, the second switch and the fourth switch are connectedin series between the first power supply terminal and the second powersupply terminal, and a second output terminal is connected electricallybetween the second switch and the fourth switch; a first phase terminalwhich receives a first phase output signal from a pulse width modulation(PWM) signal generator subsystem; a second phase terminal which receivesa second phase output signal from the PWM signal generator; a digitalstate machine which generates timing signals based on the first phaseoutput signal and the second phase output signal and outputs the timingsignals to the switches of the H-bridge circuit to control the switchesto turn on and off in a sequence such that the H-bridge circuit outputsan AC drive signal to the resonant circuit to drive the resonant circuitto generate and transmit the ultrasonic waves, wherein the sequencecomprises a free-float period in which the first switch and the secondswitch are turned off and the third switch and the fourth switch areturned on in order to dissipate energy stored by the resonant circuit; acurrent sensor which incorporates; a first current sense resistor whichis connected in series between the first switch and the first powersupply terminal; a first voltage sensor which measures the voltage dropacross the first current sense resistor and provides a first voltageoutput which is indicative of the current flowing through the firstcurrent sense resistor; a second current sense resistor which isconnected in series between the second switch and the first power supplyterminal; a second voltage sensor which measures the voltage drop acrossthe second current sensor resistor and provides a second voltage outputwhich is indicative of the current flowing through the second currentsense resistor; and a current sensor output terminal which provides anrms output voltage relative to around which is equivalent to the firstvoltage output and the second voltage output, wherein the rms outputvoltage is indicative of an rms current flowing through the first switchor the second switch and the current flowing through the resonantcircuit which is connected between the first output terminal and thesecond output terminal; and a second microchip connected to the firstmicrochip to control the H-bridge circuit to generate the AC drivesignal, wherein the second microchip is a single unit which comprises aplurality of interconnected embedded components and subsystemscomprising: an oscillator which generates: a main clock signal, a firstphase clock signal which is high for a first time during the positivehalf-period of the main clock signal and low during the negativehalf-period of the main clock signal, and a second phase clock signalwhich is high for a second time during the negative half-period of themain clock signal and low during the positive half-period of the mainclock signal, wherein the phases of the first phase clock signal and thesecond phase clock signal are centre aligned; the pulse width modulationPWM signal generator subsystem, wherein the PWM signal generatorsubsystem comprises: a delay locked loop which generates a doublefrequency clock signal using the first phase clock signal and the secondphase clock signal, the double frequency clock signal being double thefrequency of the main clock signal, wherein the delay locked loopcontrols the rising edge of the first phase clock signal and the secondphase clock signal to be synchronous with the rising edge of the doublefrequency clock signal, and wherein the delay locked loop adjusts thefrequency and the duty cycle of the first phase clock signal and thesecond phase clock signal in response to a driver control signal toproduce a first phase output signal and a second phase output signal,wherein the first phase output signal and the second phase output signalare configured to drive the H-bridge circuit to generate an AC drivesignal to drive the resonant circuit; a first phase output signalterminal which outputs the first phase output signal to the H-bridgecircuit; a second phase output signal terminal which outputs the secondphase output signal to the H-bridge circuit; a feedback input terminalwhich receives a feedback signal from the H-bridge circuit, the feedbacksignal being indicative of a parameter of the operation of the H-bridgecircuit or the AC drive signal when the H-bridge circuit is driving theresonant circuit with the AC drive signal; an analogue to digitalconverter (ADC) subsystem comprising: a plurality of ADC input terminalswhich receive a plurality of respective analogue signals, wherein oneADC input terminal of the plurality of ADC input terminals is connectedto the feedback input terminal such that the ADC subsystem receives thefeedback signal from the H-bridge circuit, and wherein the ADC subsystemsamples analogue signals received at the plurality of ADC inputterminals at a sampling frequency which is proportional to the frequencyof the main clock signal and the ADC subsystem generates ADC digitalsignals using the sampled analogue signals; a digital processorsubsystem which receives the ADC digital signals from the ADC subsystemand processes the ADC digital signals to generate the driver controlsignal, wherein the digital processor subsystem communicates the drivercontrol signal to the PWM signal generator subsystem to control the PWMsignal generator subsystem; and a digital to analogue converter (DAC)subsystem comprising: a digital to analogue converter (DAC) whichconverts a digital control signal generated by the digital processorsubsystem into an analogue voltage control signal to control a voltageregulator circuit which generates a voltage for modulation by theH-bridge circuit; and a DAC output terminal which outputs the analoguevoltage control signal to control the voltage regulator circuit togenerate a predetermined voltage for modulation by the H-bridge circuitto drive the resonant circuit in response to feedback signals which areindicative of the operation of the resonant circuit.
 17. The apparatusof claim 16, wherein the apparatus further comprises: a boost convertercircuit which is configured to increase the voltage of a power supply toa boost voltage in response to the analogue voltage output signal fromthe DAC output terminal, wherein the boost converter circuit providesthe boost voltage at the first power supply terminal such that the boostvoltage is modulated by the switching of the switches of the H-bridgecircuit.
 18. The apparatus of claim 16, wherein the current sensorsenses the current flowing through the resonant circuit during thefree-float period and the digital state machine adapts the timingsignals to switch on either the first switch or the second switch whenthe current sensor senses that the current flowing through the resonantcircuit during the free-float period is zero.
 19. The apparatus of claim16, wherein, during a setup phase of operation of the apparatus, thesecond microchip: measures the length of time taken for the currentflowing through the resonant circuit to fall to zero when the firstswitch and the second switch are turned off and the third switch and thefourth switch are turned on; and sets the length of time of thefree-float period to be equal to the measured length of time.